A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-level Computation

Abstract

General purpose computing architectures are being called on to work on amore diverse application mix every day. This has been fueled by the needfor reduced time to market and economies of scale that are the hallmarksof software on general purpose microprocessors. As this application mixexpands, application domains such as bit-level computation, which hasprimarily been the domain of ASICs and FPGAs, will need to be effectivelyhandled by general purpose hardware. Examples of bit-level applicationsinclude Ethernet framing, forward error correction encoding/decoding, andefficient state machine implementation.In this paper we compare how differing computational structures such asASICs, FPGAs, tiled architectures, and superscalar microprocessors areable to compete on bit-level communication applications. A quantitativecomparison in terms of absolute performance and performance per area willbe presented. These results show that although modest gains~(2-3x) inabsolute performance can be achieved when using FPGAs versus tunedmicroprocessor implementations, it is the significantly larger gains~(2-3orders of magnitude) that can be achieved in performance per area thatwill motivate work on supporting bit-level computation in a generalpurpose fashion in the future.