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Advanced engineered substrates for the integration of lattice-mismatched materials with silicon

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dc.contributor.advisor Eugene A. Fitzgerald. en_US
dc.contributor.author Isaacson, David Michael, 1976- en_US
dc.contributor.other Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. en_US
dc.date.accessioned 2007-02-21T13:08:01Z
dc.date.available 2007-02-21T13:08:01Z
dc.date.copyright 2006 en_US
dc.date.issued 2006 en_US
dc.identifier.uri http://hdl.handle.net/1721.1/36214
dc.description Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2006. en_US
dc.description Includes bibliographical references (p. 164-171). en_US
dc.description.abstract The dramatic advances in Si/SiO2-based microelectronic processing witnessed over the past several decades can largely be attributed to relatively material-independent device scaling. However, with physical and economic limitations to the continued scaling of such devices appearing on the horizon, it is likely that near-term advances will come from the integration of novel and previously underrepresented materials. One of the most promising ways to enhance performance comes from the integration of judiciously chosen lattice-mismatched materials with Si. However, the integration of such structures typically poses significant technical challenges. The work contained in this thesis seeks to address several of these important issues, primarily through the use of relaxed, graded SiGe buffers on Si (i.e. Vx[Si1-xGex]/Si). Several new phenomena in relaxed graded SiGe buffers are developed in this thesis. A rise in threading dislocation density was observed in high-Ge content relaxed graded SiGe layers grown at relatively high temperatures, which was attributed to dislocation nucleation. This observation is contrary to conventional graded buffer theory in which high growth temperatures are expected to result in reduced threading dislocation densities (TDDs). en_US
dc.description.abstract (cont.) Additionally, a coupling effect between the effective strain and the growth rate was observed, as evidenced by increased TDD values at reduced growth rates. This observation is attributed to reduced growth rates allowing more time for the surface to evolve (i.e. roughen) during growth, thereby trapping mobile dislocations and necessitating the nucleation of additional dislocations to continue relaxing the structure. Also detailed in this thesis is the creation of two novel CMOS-compatible platforms for high-power applications: strained-silicon on silicon (SSOS) and strained-silicon on silicon-germanium on silicon (SGOS). SSOS substrate has an epitaxially-defined, tensilely strained silicon (-Si) layer directly on bulk silicon wafer without an intermediate SiGe or oxide layer. SSOS is a homochemical heterojunction, i.e. a heterojunction defined by strain state only and not by an accompanying compositional change, and therefore in principle SSOS may ease metal-oxide-semiconductor (MOS) -Si fabrication as SiGe is absent from the structure. SGOS has an epitaxially-defined SiGe layer between the strained silicon channel and the Si substrate, which is likely necessary to prevent excessive off-state leakage in MOS devices due to overlap of the source-drain contacts and the interfacial misfit array. en_US
dc.description.abstract (cont.) The thesis concludes with a study of utilizing buried -Si layers for improving the fabrication of SSOI substrate via the hydrogen induced layer exfoliation process. Previous work involving tensile -Si.4Geo.6 layers in relaxed Ge/Vx[SiixGex/Si demonstrated that significant hydrogen gettering via the formation of strain-relieving platelets occurred within the tensile -Sio.4Ge.6 layers, leading to an overall increase in layer transfer efficiency for GOI substrate fabrication. Buried tensile -Si layers in relaxed SilGex for SSOI fabrication, however, demonstrate markedly different hydrogen gettering behavior that is dependent on a combination of both the degree of tensile strain as well the amount of damage present in the adjacent Si.xGex alloy. It was determined that a tensile strain level of approximately 1.6% in Si (corresponding to a Sio.6Ge.4-based donor structure) was needed to create sufficient engineered damage to overcome the implantation damage in the adjacent Sio.6Ge.4 layers and result in enhanced layer exfoliation. Lastly, an advanced Sio.6Geo.4-based structure which incorporated -Si layers as transfer, hydrogen gettering, and etchstop layers was demonstrated. Such a structure may prove useful for the reuse of significant portions of the original SSOI donor structure, thereby potentially speeding commercial adoption of the SSOI platform. en_US
dc.description.statementofresponsibility by David Michael Isaacson. en_US
dc.format.extent 171 p. en_US
dc.language.iso eng en_US
dc.publisher Massachusetts Institute of Technology en_US
dc.rights M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. en_US
dc.rights.uri http://dspace.mit.edu/handle/1721.1/7582
dc.subject Materials Science and Engineering. en_US
dc.title Advanced engineered substrates for the integration of lattice-mismatched materials with silicon en_US
dc.type Thesis en_US
dc.description.degree Ph.D. en_US
dc.contributor.department Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. en_US
dc.identifier.oclc 76906527 en_US


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