A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation
dc.contributor.author | Wu, Henry M. | en_US |
dc.date.accessioned | 2004-10-04T14:36:07Z | |
dc.date.available | 2004-10-04T14:36:07Z | |
dc.date.issued | 1989-04-01 | en_US |
dc.identifier.other | AIM-1119 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/6021 | |
dc.description.abstract | We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- computers can perform IEEE double-precision arithmetic. We discuss how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. We present techniques we developed to overcome a few classical drawbacks of modular arithmetic. Our architecture is suitable to and essential for the study of chaotic dynamical systems. | en_US |
dc.format.extent | 12 p. | en_US |
dc.format.extent | 2230694 bytes | |
dc.format.extent | 827297 bytes | |
dc.format.mimetype | application/postscript | |
dc.format.mimetype | application/pdf | |
dc.language.iso | en_US | |
dc.relation.ispartofseries | AIM-1119 | en_US |
dc.subject | modular arithmetic | en_US |
dc.subject | computer architecture | en_US |
dc.subject | multiprocessor | en_US |
dc.subject | sresidue number system | en_US |
dc.subject | computer arithmetic | en_US |
dc.subject | pipelining | en_US |
dc.subject | chaos | en_US |
dc.title | A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation | en_US |