Decoder Hardware Architecture for HEVC
Author(s)
Tikekar, Mehul; Huang, Chao-Tsung; Sze, Vivienne; Juvekar, Chiraag Shashikant; Chandrakasan, Anantha P.
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This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of steps in intra prediction and the introduction of a new in-loop filter. Several solutions to address these implementation challenges are discussed. As a reference, results for an HEVC decoder test chip are also presented.
Date issued
2014Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
High Efficiency Video Coding (HEVC)
Publisher
Springer-Verlag
Citation
Tikekar, Mehul, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, and Anantha Chandrakasan. “Decoder Hardware Architecture for HEVC.” High Efficiency Video Coding (HEVC) (2014): 303–341.
Version: Author's final manuscript
ISBN
978-3-319-06894-7
978-3-319-06895-4
ISSN
1558-9412