Show simple item record

dc.contributor.authorNguyen, X.S.
dc.contributor.authorYadav, S.
dc.contributor.authorLee, K.H.
dc.contributor.authorKohen, D.
dc.contributor.authorKumar, A.
dc.contributor.authorMade, R.I.
dc.contributor.authorGong, X.
dc.contributor.authorLee, K.E.
dc.contributor.authorTan, C.S.
dc.contributor.authorYoon, S.F.
dc.contributor.authorChua, S.J.
dc.contributor.authorFitzgerald, Eugene A
dc.date.accessioned2017-10-11T13:31:01Z
dc.date.available2017-10-11T13:31:01Z
dc.date.issued2017-05
dc.identifier.urihttp://hdl.handle.net/1721.1/111840
dc.description.abstractWe report on the growth of In 0.30 Ga 0.70 As channel high-electron mobility transistor (HEMT) epi-layers on a 200 mm silicon wafer by metal organic chemical vapor deposition (MOCVD). The device epi-layers were grown on a silicon substrate by using a ∼ 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded, strain relaxation layer. The achieved epitaxy has a threading dislocation density of (1 - 2) × 10[superscript 7] cm[superscript -2] and a root mean square surface roughness of 6-7 nm. The device active layers include a delta-doped InAlAs bottom barrier, a 15 nm thick InGaAs channel, a 15 nm InGaP top barrier layer and a heavily doped InGaAs contact layer. Long channel MOS-HEMT devices (LG ∼ 20 μm), were fabricated achieving a peak effective electron mobility of ∼ 3700 cm[superscript 2]/V·s.en_US
dc.publisherCS Mantechen_US
dc.relation.isversionofhttp://csmantech2017.conferencespot.org/64646gmi-1.3606545/t008-1.3607215/f008-1.3607216/0889-000037-1.3607220/ap014-1.3607221en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceOther repositoryen_US
dc.titleGrowth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOSen_US
dc.typeArticleen_US
dc.identifier.citationNguyen, X.S. et al. "Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS." 2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference), May 22-25 2017, Indian Wells, California, USA, CS Mantech, May 2017en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Materials Science and Engineeringen_US
dc.contributor.mitauthorFitzgerald, Eugene A
dc.relation.journal2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2017-10-06T13:33:36Z
dspace.orderedauthorsNguyen, X.S.; Yadav,S.; Lee, K.H.; Kohen, D.; Kumar, A.; Made, R.I.; Gong, X.; Lee, K.E.; Tan, C.S.; Yoon, S.F.; Fitzgerald, E.; Chua, S. J.en_US
dspace.embargo.termsNen_US
dc.identifier.orcidhttps://orcid.org/0000-0002-1891-1959
mit.licenseOPEN_ACCESS_POLICYen_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record