dc.contributor.author | Nguyen, X.S. | |
dc.contributor.author | Yadav, S. | |
dc.contributor.author | Lee, K.H. | |
dc.contributor.author | Kohen, D. | |
dc.contributor.author | Kumar, A. | |
dc.contributor.author | Made, R.I. | |
dc.contributor.author | Gong, X. | |
dc.contributor.author | Lee, K.E. | |
dc.contributor.author | Tan, C.S. | |
dc.contributor.author | Yoon, S.F. | |
dc.contributor.author | Chua, S.J. | |
dc.contributor.author | Fitzgerald, Eugene A | |
dc.date.accessioned | 2017-10-11T13:31:01Z | |
dc.date.available | 2017-10-11T13:31:01Z | |
dc.date.issued | 2017-05 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/111840 | |
dc.description.abstract | We report on the growth of In 0.30 Ga 0.70 As channel high-electron mobility transistor (HEMT) epi-layers on a 200 mm silicon wafer by metal organic chemical vapor deposition (MOCVD). The device epi-layers were grown on a silicon substrate by using a ∼ 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded, strain relaxation layer. The achieved epitaxy has a threading dislocation density of (1 - 2) × 10[superscript 7] cm[superscript -2] and a root mean square surface roughness of 6-7 nm. The device active layers include a delta-doped InAlAs bottom barrier, a 15 nm thick InGaAs channel, a 15 nm InGaP top barrier layer and a heavily doped InGaAs contact layer. Long channel MOS-HEMT devices (LG ∼ 20 μm), were fabricated achieving a peak effective electron mobility of ∼ 3700 cm[superscript 2]/V·s. | en_US |
dc.publisher | CS Mantech | en_US |
dc.relation.isversionof | http://csmantech2017.conferencespot.org/64646gmi-1.3606545/t008-1.3607215/f008-1.3607216/0889-000037-1.3607220/ap014-1.3607221 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Other repository | en_US |
dc.title | Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Nguyen, X.S. et al. "Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS." 2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference), May 22-25 2017, Indian Wells, California, USA, CS Mantech, May 2017 | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Materials Science and Engineering | en_US |
dc.contributor.mitauthor | Fitzgerald, Eugene A | |
dc.relation.journal | 2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference) | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dc.date.updated | 2017-10-06T13:33:36Z | |
dspace.orderedauthors | Nguyen, X.S.; Yadav,S.; Lee, K.H.; Kohen, D.; Kumar, A.; Made, R.I.; Gong, X.; Lee, K.E.; Tan, C.S.; Yoon, S.F.; Fitzgerald, E.; Chua, S. J. | en_US |
dspace.embargo.terms | N | en_US |
dc.identifier.orcid | https://orcid.org/0000-0002-1891-1959 | |
mit.license | OPEN_ACCESS_POLICY | en_US |