| dc.contributor.author | Yu, Xiangyao | |
| dc.contributor.author | Devadas, Srinivas | |
| dc.date.accessioned | 2018-03-29T18:44:46Z | |
| dc.date.available | 2018-03-29T18:44:46Z | |
| dc.date.issued | 2016-03 | |
| dc.date.submitted | 2015-10 | |
| dc.identifier.isbn | 978-1-4673-9524-3 | |
| dc.identifier.uri | http://hdl.handle.net/1721.1/114457 | |
| dc.description.abstract | A new memory coherence protocol, Tardis, is proposed. Tardis uses timestamp counters representing logical time as well as physical time to order memory operations and enforce sequential consistency in any type of shared memory system. Tardis is unique in that as compared to the widely-adopted directory coherence protocol, and its variants, it completely avoids multicasting and only requires O(log N) storage per cache block for an N-core system rather than O(N) sharer information. Tardis is simpler and easier to reason about, yet achieves similar performance to directory protocols on a wide range of benchmarks run on 16, 64 and 256 cores. | en_US |
| dc.language.iso | en_US | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1109/PACT.2015.12 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | MIT Web Domain | en_US |
| dc.title | Tardis: Time Traveling Coherence Algorithm for Distributed Shared Memory | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Yu, Xiangyao, and Srinivas Devadas. "Tardis: Time Traveling Coherence Algorithm for Distributed Shared Memory." 2015 International Conference on Parallel Architecture and Compilation (PACT), 18-21 October, 2015, San Francisco, California, IEEE, 2015, pp. 227–40. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.contributor.mitauthor | Yu, Xiangyao | |
| dc.contributor.mitauthor | Devadas, Srinivas | |
| dc.relation.journal | 2015 International Conference on Parallel Architecture and Compilation (PACT) | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
| eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
| dspace.orderedauthors | Yu, Xiangyao; Devadas, Srinivas | en_US |
| dspace.embargo.terms | N | en_US |
| dc.identifier.orcid | https://orcid.org/0000-0003-4317-3457 | |
| dc.identifier.orcid | https://orcid.org/0000-0001-8253-7714 | |
| mit.license | OPEN_ACCESS_POLICY | en_US |
