dc.contributor.author | Banerjee, Utsav | |
dc.contributor.author | Das, Siddharth | |
dc.contributor.author | Chandrakasan, Anantha P | |
dc.date.accessioned | 2020-11-20T18:09:20Z | |
dc.date.available | 2020-11-20T18:09:20Z | |
dc.date.issued | 2020-10 | |
dc.date.submitted | 2020-09 | |
dc.identifier.isbn | 9781728133201 | |
dc.identifier.issn | 2158-1525 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/128546 | |
dc.description.abstract | Post-quantum cryptography (PQC) is currently a growing area of research and NIST PQC Round 2 schemes are being actively analyzed and optimized for both security and efficiency. In this work, we repurpose the cryptographic accelerators in an energy-efficient pre-quantum TLS crypto-processor to implement post-quantum key encapsulation schemes SIKE, Frodo and ThreeBears and signature scheme SPHINCS + . We utilize the modular arithmetic unit inside the elliptic curve cryptography accelerator to implement SIKE, while we use the AES-256 and SHA2-256 hardware primitives to substitute SHA3-256 and SHAKE-256 computations and accelerate the other three protocols. We accelerate the most computationally expensive components of these PQC protocols in hardware, thereby achieving up to an order of magnitude improvement in energy-efficiency over software implementations. | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/iscas45731.2020.9180550 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Banerjee, Utsav | en_US |
dc.title | Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Banerjee, Utsav et al. "Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor." IEEE International Symposium on Circuits and Systems (ISCAS), October 2020, Sevilla, Spain, Institute of Electrical and Electronics Engineers (IEEE), October 2020. © 2020 IEEE | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.relation.journal | IEEE International Symposium on Circuits and Systems (ISCAS) | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dspace.date.submission | 2020-11-17T03:24:44Z | |
mit.license | OPEN_ACCESS_POLICY | |
mit.metadata.status | Complete | |