Design, modeling, and simulation of a Compact Optoelectronic Neural Coprocessor
Name
72690362-MIT.pdf
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Full printable version
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12.69 MB
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615e185b43ad6bb77a0c21f08f486f5c
Author(s)
Simpkins, Travis L. (Travis Lee), 1977-
Advisor(s)
Cardinal Warde.
Alternative Title
CONCOP
Date Issued
2006
Publisher
Massachusetts Institute of Technology
Abstract
Microprocessors have substantially increased in speed and computational power over the past two decades. However, they still are unable to solve certain classes of problems efficiently, particularly those which involve the analysis of large noisy data sets such as the case of image processing, feature extraction, and pattern recognition. Substantial research has focused on using neural network algorithms to process this type of data with much success. Most of this effort, however, has resulted in sophisticated neural network-based software algorithms rather than physical neural network hardware. Consequently, most neural network-type processing systems today consist of neural algorithms running on traditional sequential (i.e. Intel-based) microprocessors rather than on actual neurocomputers, and thus achieve less than optimal performance. The objective of the Compact Optoelectronic Neural Coprocessor (CONCOP) project is to build a compact, pixilated, parallel optoelectronic processor capable of running neural network-type algorithms in native hardware.
(cont.) While much of the past research on the project has focused on designing and implementing the microphotonics and optoelectronics required for interlayer communication within the system, the work presented in this thesis will begin by focusing on the computational components, particularly the mixed-signal integrated circuits located in each pixel. After the circuits have been designed, a progressive training and simulation environment will be developed based on hierarchal system models which provide accurate, timely, and efficient performance estimates of the CONCOP while it is still in the pre-integration stage. Using this simulation platform, several simulations of the CONCOP will be performed to demonstrate the flexibility of the environment and to better understand the scalability and fault-tolerance aspects of the CONCOP. The results of a test chip containing the fundamental circuit components will also be presented.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2006.
Includes bibliographical references (p. 169-174).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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