A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
Name
Kim-2009-A 10-Gb_s Compact Lo.pdf
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Author(s)
Kim, Byeong-Su
Liu, Yong
Dickson, Timothy O.
Bulzacchelli, John F.
Friedman, Daniel J.
Date Issued
December 2009
Journal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers
Citation
Byungsub Kim et al. “A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.” Solid-State Circuits, IEEE Journal of 44.12 (2009): 3526-3538. © 2009 Institute of Electrical and Electronics Engineers
Version
Final published version
Abstract
A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many post cursors without paying the power and area penalty that would be incurred with a conventional high tap-count DFE. Equalization capabilities of the compact I/O at 10 Gb/s are demonstrated over various channels including conventional chip-to-chip and backplane links with half-baud losses of up to 27 dB. Finally, a transmitter-receiver pair operating over a 40-mm on-chip emulated silicon carrier channel was demonstrated to 8.9 Gb/s, at a link power efficiency of 1.9 mW/Gb/s.
Subjects
backplane channel communication
chip-to-chip communication
compact I/O
continuous-time IIR filter
decision feedback equalizer
serial link
silicon carrier links
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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DOI of Published Version
http://dx.doi.org/10.1109/jssc.2009.2031015
