Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Author: Chen, C. L.; Chen, C. K.; Yost, D.-R.; Knecht, J. M.; Wyatt, P. W.; Burns, J. A.; Warner, K.; Gouker, P. M.; Healey, P.; Wheeler, B.; Keast, C. L.

Citable URI: http://hdl.handle.net/1721.1/58963

Department: Lincoln Laboratory

Publisher: Institute of Electrical and Electronics Engineers

Date Issued: 2009-02

Abstract:

RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved.

URI: http://hdl.handle.net/1721.1/58963

ISBN: 978-1-4244-3940-9

Citation: Chen, C.L. et al. “Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers.” Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on. 2009. 1-4. © 2009 Institute of Electrical and Electronics Engineers.

Version: Final published version

Terms of Use: Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.

Published As: http://dx.doi.org/10.1109/SMIC.2009.4770536

Journal: IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09

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