Low-overhead hard real-time aware interconnect network router
Author(s)Kinsy, Michel A.; Devadas, Srinivas
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The increasing complexity of embedded systems is accelerating the use of multicore processors in these systems. This trend gives rise to new problems such as the sharing of on-chip network resources among hard real-time and normal best effort data traffic. We propose a network-on-chip router that provides predictable and deterministic communication latency for hard real-time data traffic while maintaining high concurrency and throughput for best-effort/general-purpose traffic with minimal hardware overhead. The proposed router requires less area than non-interfering networks, and provides better Quality of Service (QoS) in terms of predictability and determinism to hard real-time traffic than priority-based routers. We present a deadlock-free algorithm for decoupled routing of the two types of traffic. We compare the area and power estimates of three different router architectures with various QoS schemes using the IBM 45-nm SOI CMOS technology cell library. Performance evaluations are done using three realistic benchmark applications: a hybrid electric vehicle application, a utility grid connected photovoltaic converter system, and a variable speed induction motor drive application.
DepartmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Proceedings of the 2014 IEEE High Performance Extreme Computing Conference (HPEC)
Institute of Electrical and Electronics Engineers (IEEE)
Kinsy, Michel A., and Srinivas Devadas. “Low-Overhead Hard Real-Time Aware Interconnect Network Router.” 2014 IEEE High Performance Extreme Computing Conference (HPEC) (September 2014).
Author's final manuscript