Show simple item record

dc.contributor.authorPacella, Nan Y.
dc.contributor.authorBulsara, Mayank
dc.contributor.authorDrazek, Charlotte
dc.contributor.authorGuiot, Eric
dc.contributor.authorFitzgerald, Eugene A.
dc.date.accessioned2016-03-28T17:11:59Z
dc.date.available2016-03-28T17:11:59Z
dc.date.issued2015-05
dc.date.submitted2015-04
dc.identifier.issn2162-8769
dc.identifier.issn2162-8777
dc.identifier.urihttp://hdl.handle.net/1721.1/101889
dc.description.abstractThe Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915°C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO[subscript 2] and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES.en_US
dc.description.sponsorshipUnited States. Defense Advanced Research Projects Agency. COSMOS Programen_US
dc.description.sponsorshipUnited States. Office of Naval Research (Contract N00014-07-C-0629)en_US
dc.language.isoen_US
dc.publisherElectrochemical Societyen_US
dc.relation.isversionofhttp://dx.doi.org/10.1149/2.0221507jssen_US
dc.rightsCreative Commons Attribution-NonCommercial-NoDerivs Licenseen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/en_US
dc.sourceElectrochemical Societyen_US
dc.titleFabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substratesen_US
dc.typeArticleen_US
dc.identifier.citationPacella, N. Y., M. T. Bulsara, C. Drazek, E. Guiot, and E. A. Fitzgerald. “Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates.” ECS Journal of Solid State Science and Technology 4, no. 7 (May 7, 2015): P258–P264.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Materials Processing Centeren_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Materials Science and Engineeringen_US
dc.contributor.mitauthorPacella, Nan Y.en_US
dc.contributor.mitauthorBulsara, Mayanken_US
dc.contributor.mitauthorFitzgerald, Eugene A.en_US
dc.relation.journalECS Journal of Solid State Science and Technologyen_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsPacella, N. Y.; Bulsara, M. T.; Drazek, C.; Guiot, E.; Fitzgerald, E. A.en_US
dc.identifier.orcidhttps://orcid.org/0000-0002-1891-1959
mit.licensePUBLISHER_CCen_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record