InGaAs/InAs heterojunction vertical nanowire tunnel FETs fabricated by a top-down approach
Author(s)Zhao, Xin; Vardi, Alon; del Alamo, Jesus A.
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We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at V[subscript ds]= 0.3 V is obtained over 2 decades of current. On the same device, I[subscript on]= 0.27 μA/μm is extracted at V[subscript dd]= 0.3 V with a fixed I[subscript off]= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials.
DepartmentMassachusetts Institute of Technology. Department of Materials Science and Engineering; Massachusetts Institute of Technology. Microsystems Technology Laboratories
Proceedings of the 2014 IEEE International Electron Devices Meeting
Institute of Electrical and Electronics Engineers (IEEE)
Zhao, Xin, Alon Vardi, and Jesus A. del Alamo. “InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs Fabricated by a Top-down Approach.” 2014 IEEE International Electron Devices Meeting (December 2014).
Author's final manuscript