InGaAs/InAs heterojunction vertical nanowire tunnel FETs fabricated by a top-down approach

Abstract

We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at V[subscript ds]= 0.3 V is obtained over 2 decades of current. On the same device, I[subscript on]= 0.27 μA/μm is extracted at V[subscript dd]= 0.3 V with a fixed I[subscript off]= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials.