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dc.contributor.authorElfadel, Ibrahim M.
dc.contributor.authorZhang, Zheng
dc.contributor.authorEl Moselhy, Tarek Ali
dc.contributor.authorDaniel, Luca
dc.date.accessioned2017-04-25T19:05:25Z
dc.date.available2017-04-25T19:05:25Z
dc.date.issued2013-09
dc.identifier.issn0278-0070
dc.identifier.issn1937-4151
dc.identifier.urihttp://hdl.handle.net/1721.1/108401
dc.description.abstractUncertainties have become a major concern in integrated circuit design. In order to avoid the huge number of repeated simulations in conventional Monte Carlo flows, this paper presents an intrusive spectral simulator for statistical circuit analysis. Our simulator employs the recently developed generalized polynomial chaos expansion to perform uncertainty quantification of nonlinear transistor circuits with both Gaussian and non-Gaussian random parameters. We modify the nonintrusive stochastic collocation (SC) method and develop an intrusive variant called stochastic testing (ST) method. Compared with the popular intrusive stochastic Galerkin (SG) method, the coupled deterministic equations resulting from our proposed ST method can be solved in a decoupled manner at each time point. At the same time, ST requires fewer samples and allows more flexible time step size controls than directly using a nonintrusive SC solver. These two properties make ST more efficient than SG and than existing SC methods, and more suitable for time-domain circuit simulation. Simulation results of several digital, analog and RF circuits are reported. Since our algorithm is based on generic mathematical models, the proposed ST algorithm can be applied to many other engineering problems.en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/TCAD.2013.2263039en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceProf. Daniel via Phoebe Ayersen_US
dc.titleStochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaosen_US
dc.typeArticleen_US
dc.identifier.citationZhang, Zheng; El-Moselhy, Tarek A.; Elfadel, Ibrahim M. and Daniel, Luca. "Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 10 (October 2013): 1533-1545. © 2013 Institute of Electrical and Electronics Engineers (IEEE)en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Aeronautics and Astronauticsen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverDaniel, Lucaen_US
dc.contributor.mitauthorZhang, Zheng
dc.contributor.mitauthorEl Moselhy, Tarek Ali
dc.contributor.mitauthorDaniel, Luca
dc.relation.journalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsZhang, Zheng; El-Moselhy, Tarek A.; Elfadel, Ibrahim M.; Daniel, Lucaen_US
dspace.embargo.termsNen_US
dc.identifier.orcidhttps://orcid.org/0000-0002-5880-3151
mit.licenseOPEN_ACCESS_POLICYen_US


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