A Fully-Integrated Energy-Efficient H.265/HEVC Decoder with eDRAM for Wearable Devices
Author(s)Tikekar, Mehul; Sze, Vivienne; Chandrakasan, Anantha P
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Data movement to and from off-chip memory dominates energy consumption in most video decoders, with DRAM accesses consuming 2.8x-6x more energy than the processing itself. We present a H.265/HEVC video decoder with embedded DRAM (eDRAM) as main memory. We propose the following techniques to optimize data movement and reduce the power consumption of eDRAM: 1) lossless compression is used to store reference frames in 2x fewer eDRAM banks, reducing refresh power by 33%; 2) eDRAM banks are powered up on-demand to further reduce refresh power by 33%; 3) syntax elements are distributed to four decoder cores in a partially compressed form to reduce decoupling buffer power by 4x. These approaches reduce eDRAM power by 2x in a fully-integrated H.265/HEVC decoder with the lowest reported system power. The decoder chip requires no external components and consumes 24.9 – 30.6mW for 1920x1080 video at 24-50 fps.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology Laboratories
2017 IEEE Symposia on VLSI Technology and Circuits
IEEE/Japan Society of Applied Physics
Tikekar, Mehul, Vivienne Sze, and Anantha Chandrakasan. "A Fully-Integrated Energy-Efficient H.265/HEVC Decoder with eDRAM for Wearable Devices." In Digest of Technical Papers, 2017 Symposia on VLSI Circuits, Kyoto, Japan, June 5-8, 2017. IEEE.
Author's final manuscript
Session 17, C17-4