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dc.contributor.authorEmer, Joel
dc.contributor.authorJeffrey, Mark Christopher
dc.contributor.authorSubramanian, Suvinay
dc.contributor.authorYan, Cong
dc.contributor.authorSanchez, Daniel
dc.date.accessioned2017-10-23T19:01:15Z
dc.date.available2017-10-23T19:01:15Z
dc.date.issued2015-12
dc.identifier.issn978-1-4503-4034-2
dc.identifier.urihttp://hdl.handle.net/1721.1/111962
dc.description.abstractWe present Swarm, a novel architecture that exploits ordered irregular parallelism, which is abundant but hard to mine with current software and hardware techniques. In this architecture, programs consist of short tasks with programmer-specified timestamps. Swarm executes tasks speculatively and out of order, and efficiently speculates thousands of tasks ahead of the earliest active task to uncover ordered parallelism. Swarm builds on prior TLS and HTM schemes, and contributes several new techniques that allow it to scale to large core counts and speculation windows, including a new execution model, speculation-aware hardware task management, selective aborts, and scalable ordered commits. We evaluate Swarm on graph analytics, simulation, and database benchmarks. At 64 cores, Swarm achieves 51--122× speedups over a single-core system, and out-performs software-only parallel algorithms by 3--18×.en_US
dc.description.sponsorshipNational Science Foundation (U.S.) (Award CAREER-145299)en_US
dc.language.isoen_US
dc.publisherAssociation for Computing Machinery (ACM)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1145/2830772.2830777en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT Web Domainen_US
dc.titleA scalable architecture for ordered parallelismen_US
dc.typeArticleen_US
dc.identifier.citationJeffrey, Mark C. et al. “A Scalable Architecture for Ordered Parallelism.” Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48), December 5-9, 2015, Waikiki, Hawaii, USA, Association for Computing Machinery (ACM), December 2015 © 2015 Association for Computing Machinery (ACM)en_US
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratoryen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.mitauthorJeffrey, Mark Christopher
dc.contributor.mitauthorSubramanian, Suvinay
dc.contributor.mitauthorYan, Cong
dc.contributor.mitauthorSanchez Martin, Daniel
dc.relation.journalProceedings of the 48th International Symposium on Microarchitecture (MICRO-48)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsJeffrey, Mark C.; Subramanian, Suvinay; Yan, Cong; Emer, Joel; Sanchez, Danielen_US
dspace.embargo.termsNen_US
dc.identifier.orcidhttps://orcid.org/0000-0003-4816-0356
dc.identifier.orcidhttps://orcid.org/0000-0001-7701-8303
dc.identifier.orcidhttps://orcid.org/0000-0003-2738-1803
dc.identifier.orcidhttps://orcid.org/0000-0002-2453-2904
dspace.mitauthor.errortrue
mit.licenseOPEN_ACCESS_POLICYen_US


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