dc.contributor.author | Beckmann, Nathan Zachary | |
dc.contributor.author | Sanchez, Daniel | |
dc.date.accessioned | 2018-01-12T19:31:40Z | |
dc.date.available | 2018-01-12T19:31:40Z | |
dc.date.issued | 2016-04 | |
dc.date.submitted | 2016-03 | |
dc.identifier.isbn | 978-1-4673-9211-2 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/113093 | |
dc.description.abstract | Modern processors use high-performance cache replacement policies that outperform traditional alternatives like least-recently used (LRU). Unfortunately, current cache models do not capture these high-performance policies as most use stack distances, which are inherently tied to LRU or its variants. Accurate predictions of cache performance enable many optimizations in multicore systems. For example, cache partitioning uses these predictions to divide capacity among applications in order to maximize performance, guarantee quality of service, or achieve other system objectives. Without an accurate model for high-performance replacement policies, these optimizations are unavailable to modern processors. We present a new probabilistic cache model designed for high-performance replacement policies. It uses absolute reuse distances instead of stack distances, and models replacement policies as abstract ranking functions. These innovations let us model arbitrary age-based replacement policies. Our model achieves median error of less than 1% across several high-performance policies on both synthetic and SPEC CPU2006 benchmarks. Finally, we present a case study showing how to use the model to improve shared cache performance. | en_US |
dc.description.sponsorship | National Science Foundation (U.S.) (Grant CCF-1318384) | en_US |
dc.description.sponsorship | Qatar Computing Research Institute | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/HPCA.2016.7446067 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | MIT Web Domain | en_US |
dc.title | Modeling cache performance beyond LRU | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Beckmann, Nathan, and Daniel Sanchez. "Modeling Cache Performance beyond LRU." 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 12-16 March, 2106, Barcelona, Spain, IEEE, 2016, pp. 225–36. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.mitauthor | Beckmann, Nathan Zachary | |
dc.contributor.mitauthor | Sanchez, Daniel | |
dc.relation.journal | 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dspace.orderedauthors | Beckmann, Nathan; Sanchez, Daniel | en_US |
dspace.embargo.terms | N | en_US |
dc.identifier.orcid | https://orcid.org/0000-0002-6057-9769 | |
mit.license | OPEN_ACCESS_POLICY | en_US |