Show simple item record

dc.contributor.authorBeckmann, Nathan Zachary
dc.contributor.authorSanchez, Daniel
dc.date.accessioned2018-01-12T19:31:40Z
dc.date.available2018-01-12T19:31:40Z
dc.date.issued2016-04
dc.date.submitted2016-03
dc.identifier.isbn978-1-4673-9211-2
dc.identifier.urihttp://hdl.handle.net/1721.1/113093
dc.description.abstractModern processors use high-performance cache replacement policies that outperform traditional alternatives like least-recently used (LRU). Unfortunately, current cache models do not capture these high-performance policies as most use stack distances, which are inherently tied to LRU or its variants. Accurate predictions of cache performance enable many optimizations in multicore systems. For example, cache partitioning uses these predictions to divide capacity among applications in order to maximize performance, guarantee quality of service, or achieve other system objectives. Without an accurate model for high-performance replacement policies, these optimizations are unavailable to modern processors. We present a new probabilistic cache model designed for high-performance replacement policies. It uses absolute reuse distances instead of stack distances, and models replacement policies as abstract ranking functions. These innovations let us model arbitrary age-based replacement policies. Our model achieves median error of less than 1% across several high-performance policies on both synthetic and SPEC CPU2006 benchmarks. Finally, we present a case study showing how to use the model to improve shared cache performance.en_US
dc.description.sponsorshipNational Science Foundation (U.S.) (Grant CCF-1318384)en_US
dc.description.sponsorshipQatar Computing Research Instituteen_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/HPCA.2016.7446067en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT Web Domainen_US
dc.titleModeling cache performance beyond LRUen_US
dc.typeArticleen_US
dc.identifier.citationBeckmann, Nathan, and Daniel Sanchez. "Modeling Cache Performance beyond LRU." 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 12-16 March, 2106, Barcelona, Spain, IEEE, 2016, pp. 225–36.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.mitauthorBeckmann, Nathan Zachary
dc.contributor.mitauthorSanchez, Daniel
dc.relation.journal2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsBeckmann, Nathan; Sanchez, Danielen_US
dspace.embargo.termsNen_US
dc.identifier.orcidhttps://orcid.org/0000-0002-6057-9769
mit.licenseOPEN_ACCESS_POLICYen_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record