dc.contributor.author | Vardi, Assaf | |
dc.contributor.author | Lin, Jian | |
dc.contributor.author | Lu, W. | |
dc.contributor.author | Zhao, X. | |
dc.contributor.author | Fernando Saavedra, Amalia Luisa | |
dc.contributor.author | del Alamo, Jesus A | |
dc.date.accessioned | 2019-05-20T16:40:56Z | |
dc.date.available | 2019-05-20T16:40:56Z | |
dc.date.issued | 2017-11 | |
dc.identifier.issn | 0894-6507 | |
dc.identifier.issn | 1558-2345 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/121163 | |
dc.description.abstract | We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl[subscript 3]/SiCl[subscript 4]/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with L[subscript g] = 20 nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained. | en_US |
dc.description.sponsorship | United States. Defense Threat Reduction Agency (Grant HDTRA1-14-1-0057) | en_US |
dc.description.sponsorship | National Science Foundation (U.S.) (Grant E3S-STC-0939514) | en_US |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | 10.1109/tsm.2017.2753141 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | MIT web domain | en_US |
dc.title | A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Vardi, A. et al. "A Si Compatible Fabriacaton Process for Scaled Self-Aligned InGaAs FinFets." IEEE Transactions on Semiconductor Manufacturing, 30, 4 (November 2017): 468 - 474 © 2017 IEEE | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.relation.journal | IEEE Transactions on Semiconductor Manufacturing | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dc.date.updated | 2019-05-17T15:33:04Z | |
dspace.date.submission | 2019-05-17T15:33:07Z | |
mit.journal.volume | 30 | en_US |
mit.journal.issue | 4 | en_US |