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dc.contributor.authorVardi, Assaf
dc.contributor.authorLin, Jian
dc.contributor.authorLu, W.
dc.contributor.authorZhao, X.
dc.contributor.authorFernando Saavedra, Amalia Luisa
dc.contributor.authordel Alamo, Jesus A
dc.date.accessioned2019-05-20T16:40:56Z
dc.date.available2019-05-20T16:40:56Z
dc.date.issued2017-11
dc.identifier.issn0894-6507
dc.identifier.issn1558-2345
dc.identifier.urihttps://hdl.handle.net/1721.1/121163
dc.description.abstractWe have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl[subscript 3]/SiCl[subscript 4]/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with L[subscript g] = 20 nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained.en_US
dc.description.sponsorshipUnited States. Defense Threat Reduction Agency (Grant HDTRA1-14-1-0057)en_US
dc.description.sponsorshipNational Science Foundation (U.S.) (Grant E3S-STC-0939514)en_US
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionof10.1109/tsm.2017.2753141en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT web domainen_US
dc.titleA Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETsen_US
dc.typeArticleen_US
dc.identifier.citationVardi, A. et al. "A Si Compatible Fabriacaton Process for Scaled Self-Aligned InGaAs FinFets." IEEE Transactions on Semiconductor Manufacturing, 30, 4 (November 2017): 468 - 474 © 2017 IEEEen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.relation.journalIEEE Transactions on Semiconductor Manufacturingen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dc.date.updated2019-05-17T15:33:04Z
dspace.date.submission2019-05-17T15:33:07Z
mit.journal.volume30en_US
mit.journal.issue4en_US


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