An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things
Author(s)
Banerjee, Utsav; Pathak, Abhishek; Chandrakasan, Anantha P.
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Alternative title
2.3 An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things
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Modern public key protocols, such as RSA and elliptic curve cryptography (ECC), will be rendered insecure by Shor's algorithm [1] when large-scale quantum computers are built. Therefore, cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate [1]. However, high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on resource-constrained IoT devices, which need to secure data against both present and future adversaries. To address this challenge, we present a lattice cryptography processor with configurable parameters, which enables up to two orders of magnitude energy savings and 124K-gate reduction in system area through architectural optimizations. The ASIC demonstrates multiple lattice-based protocols proposed in Round 1 of the NIST post-quantum standardization process.
Date issued
2019-03Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
2019 IEEE International Solid- State Circuits Conference (ISSCC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Banerjee, Utsav et al. "2.3 An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things." 2019 IEEE International Solid- State Circuits Conference (ISSCC), February 2019, San Francisco, California, United States, Institute of Electrical and Electronics Engineers, March 2019 © 2019 IEEE
Version: Author's final manuscript
ISSN
2376-8606
0193-6530