Generating infrastructure for FPGA-accelerated applications
Author(s)King, Myron; Khan, Asif; Agarwal, Abhinav; Arvind, Arvind
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Whether for use as the final target or simply a rapid prototyping platform, programming systems containing FPGAs is challenging. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running on the FPGA. In this paper we present a new methodology and programming model for introducing hardware-acceleration to an application running in software. The application is represented as a data-flow graph and the computation at each node in the graph is specified for execution either in software or on the FPGA using the programmer's language of choice. We have implemented an interface compiler which takes as its input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. Our methodology and compiler enable programmers to effectively exploit FPGA acceleration without ever leaving the application space.
DepartmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
2013 23rd International Conference on Field programmable Logic and Applications
Institute of Electrical and Electronics Engineers (IEEE)
King, Myron, Asif Khan, Abhinav Agarwal, Oriol Arcas and Arvind. "Generating infrastructure for FPGA-accelerated applications." Paper presented at the 2013 23rd International Conference on Field programmable Logic and Applications, Porto, Portugal, 2-4 September 2013.
Author's final manuscript