dc.contributor.author | Piedra, Daniel | |
dc.contributor.author | Palacios, Tomas | |
dc.contributor.author | Shepard, Kenneth L. | |
dc.date.accessioned | 2019-07-10T15:49:02Z | |
dc.date.available | 2019-07-10T15:49:02Z | |
dc.date.issued | 2017-06 | |
dc.date.submitted | 2016-12 | |
dc.identifier.issn | 0018-9200 | |
dc.identifier.issn | 1558-173X | |
dc.identifier.uri | https://hdl.handle.net/1721.1/121560 | |
dc.description.abstract | This paper presents a 40-MHz hybrid CMOS/GaN integrated multiphase DC-DC switched-inductor buck converter with a maximum 20-V input voltage. The half-bridge switches are realized using lateral AlGaN/GaN HEMTs, while the drivers and other circuitry are implemented in standard 180-nm CMOS. The interface between the CMOS and GaN dice is achieved through face-to-face bonding, reducing inductive parasitics for the connection to less than 15 pH. A capacitively coupled level shifter provides the gate drive for the high-side GaN switch using 5-V CMOS devices. The converter demonstrates 76% efficiency for 8:1 V conversion and over 60% efficiency for conversion ratios up to 16:1. | en_US |
dc.description.sponsorship | United States. Advanced Research Projects Agency-Energy (Contract DE-AR0000452) | en_US |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | 10.1109/JSSC.2017.2672986 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | other univ website | en_US |
dc.title | Hybrid CMOS/GaN 40-MHz Maximum 20-V Input DC–DC Multiphase Buck Converter | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Aklimi, Eyal, Daniel Piedra, Kevin Tien, Tomás Palacios and Kenneth L. Shepard. "Hybrid CMOS/GaN 40-MHz Maximum 20-V Input DC–DC Multiphase Buck Converter." IEEE Journal of Solid-State Circuits 52, issue 6 (June 2017): pp. 1618-1627. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.relation.journal | IEEE Journal of Solid-State Circuits | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dc.date.updated | 2019-07-01T12:45:17Z | |
dspace.date.submission | 2019-07-01T12:45:19Z | |
mit.journal.volume | 52 | en_US |
mit.journal.issue | 6 | en_US |