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dc.contributor.authorChen, Minjie
dc.contributor.authorPerreault, David J.
dc.date.accessioned2019-07-18T17:46:36Z
dc.date.available2019-07-18T17:46:36Z
dc.date.issued2019-03
dc.identifier.issn0885-8993
dc.identifier.urihttps://hdl.handle.net/1721.1/121768
dc.description.abstractSingle-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching (ZVS) at high frequencies (HF, 1-3 MHz) across universal input voltage range (85Vac-265Vac) and wide power range. The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This Multitrack concept is compatible with a wide range of existing design techniques for PFC systems. A prototype 150W, universal ac input, 12VDC output, isolated Multitrack PFC system with a power density of 50W/inch3 and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the Multitrack PFC architecture.en_US
dc.description.sponsorshipTexas Instruments Incorporateden_US
dc.description.sponsorshipCenter for Intelligent Control Systems (U.S.)en_US
dc.description.sponsorshipPrinceton University. Andlinger Center for Energy and the Environmenten_US
dc.description.sponsorshipSiebel Energy Instituteen_US
dc.language.isoen
dc.publisherIEEEen_US
dc.relation.isversionof10.1109/apec.2018.8341094en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceother univ websiteen_US
dc.titleMultitrack power factor correction architectureen_US
dc.typeArticleen_US
dc.identifier.citationChen, Minjie, Sombuddha Chakraborty and David J. Perreault. "Multitrack Power Factor Correction Architecture." IEEE Transactions on Power Electronics 34, no.3 (March 2019): pp. 2454-2466 © 2018 The Author(s)en_US
dc.contributor.departmentMassachusetts Institute of Technology. Research Laboratory of Electronicsen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.relation.journalIEEE Transactions on Power Electronicsen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2019-07-01T15:55:21Z
dspace.date.submission2019-07-01T15:55:23Z
mit.journal.volume34en_US
mit.journal.issue3en_US


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