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10 Gbps TCP/IP streams from the FPGA for the CMS DAQ eventbuilder network

dc.contributor.authorBauer, Gerry P
dc.contributor.authorBawej, T
dc.contributor.authorBehrens, U
dc.contributor.authorBranson, J
dc.contributor.authorChaze, O
dc.contributor.authorCittolin, S
dc.contributor.authorCoarasa, J A
dc.contributor.authorDarlea, Georgiana-Lavinia
dc.contributor.authorDeldicque, C
dc.contributor.authorDobson, M
dc.contributor.authorDupont, A
dc.contributor.authorErhan, S
dc.contributor.authorGigi, D
dc.contributor.authorGlege, F
dc.contributor.authorGomez-Ceballos, G
dc.contributor.authorGomez-Reino, R
dc.contributor.authorHartl, C
dc.contributor.authorHegeman, J
dc.contributor.authorHolzner, A
dc.contributor.authorMasetti, L
dc.contributor.authorMeijers, F
dc.contributor.authorMeschi, E
dc.contributor.authorMommsen, R K
dc.contributor.authorMorovic, S
dc.contributor.authorNunez-Barranco-Fernandez, C
dc.contributor.authorO'Dell, V
dc.contributor.authorOrsini, L
dc.contributor.authorOzga, W
dc.contributor.authorPaus, Christoph M. E.
dc.contributor.authorPetrucci, A
dc.contributor.authorPieri, M
dc.contributor.authorRacz, A
dc.contributor.authorRaginel, Olivier
dc.contributor.authorSakulin, H
dc.contributor.authorSani, M
dc.contributor.authorSchwick, C
dc.contributor.authorSpataru, A C
dc.contributor.authorStieger, B
dc.contributor.authorSumorok, Konstanty C
dc.contributor.authorVeverka, Jan
dc.contributor.authorWakefield, C C
dc.contributor.authorZejdl, P
dc.date.accessioned2019-07-18T20:14:25Z
dc.date.available2019-07-18T20:14:25Z
dc.date.issued2013-12
dc.date.submitted2013-11
dc.identifier.issn1748-0221
dc.identifier.urihttps://hdl.handle.net/1721.1/121774
dc.description.abstractFor the upgrade of the DAQ of the CMS experiment in 2013/2014 an interface between the custom detector Front End Drivers (FEDs) and the new DAQ eventbuilder network has to be designed. For a loss-less data collection from more then 600 FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. We present the hardware challenges and protocol modifications made to TCP in order to simplify its FPGA implementation together with a set of performance measurements which were carried out with the current prototype.en_US
dc.language.isoen
dc.publisherIOP Publishingen_US
dc.relation.isversionofhttp://dx.doi.org/10.1088/1748-0221/8/12/c12039en_US
dc.rightsCreative Commons Attribution 3.0 unported licenseen_US
dc.rights.urihttps://creativecommons.org/licenses/by/3.0/en_US
dc.sourceIOP Publishingen_US
dc.title10 Gbps TCP/IP streams from the FPGA for the CMS DAQ eventbuilder networken_US
dc.typeArticleen_US
dc.identifier.citationBauer, G. et al. "10 Gbps TCP/IP streams from the FPGA for the CMS DAQ eventbuilder network." Journal of Instrumentation 8 (December 2013): C12039 © 2013 CERNen_US
dc.contributor.departmentMassachusetts Institute of Technology. Laboratory for Nuclear Scienceen_US
dc.relation.journalJournal of Instrumentationen_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dc.date.updated2019-05-21T12:31:25Z
dspace.date.submission2019-05-21T12:31:26Z
mit.journal.volume8en_US
mit.journal.issue12en_US


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