Multitrack Power Factor Correction Architecture
Author(s)Chen, Minjie; Perreault, David J.
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Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz-4 MHz) across universal input voltage range (85 V ac-265 V ac). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12 V dc output, isolated multitrack PFC system with a power density of 50 W/in3, and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture.
DepartmentMassachusetts Institute of Technology. Research Laboratory of Electronics; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
IEEE Transactions on Power Electronics
Institute of Electrical and Electronics Engineers (IEEE)
Chen, Minjie, Sombuddha Chakraborty and David J. Perreault. "Multitrack Power Factor Correction Architecture." IEEE Transactions on Power Electronics 34, issue 3 (March 2019): 2454-2466.
Author's final manuscript
Electrical and Electronic Engineering