dc.contributor.author | Vijayaraghavan, Muralidaran | |
dc.contributor.author | Chlipala, Adam | |
dc.contributor.author | Arvind, Arvind | |
dc.contributor.author | Nirav, Dave | |
dc.date.accessioned | 2019-10-16T19:59:55Z | |
dc.date.available | 2019-10-16T19:59:55Z | |
dc.date.issued | 2015-07 | |
dc.identifier.isbn | 9783319216676 | |
dc.identifier.isbn | 9783319216683 | |
dc.identifier.issn | 0302-9743 | |
dc.identifier.issn | 1611-3349 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/122607 | |
dc.description.abstract | We present a new framework for modular verification of hardware designs in the style of the Bluespec language. That is, we formalize the idea of components in a hardware design, with well-defined input and output channels; and we show how to specify and verify components individually, with machine-checked proofs in the Coq proof assistant. As a demonstration, we verify a fairly realistic implementation of a multicore shared-memory system with two types of components: memory system and processor. Both components include nontrivial optimizations, with the memory system employing an arbitrary hierarchy of cache nodes that communicate with each other concurrently, and with the processor doing speculative execution of many concurrent read operations. Nonetheless, we prove that the combined system implements sequential consistency. To our knowledge, our memory-system proof is the first machine verification of a cache-coherence protocol parameterized over an arbitrary cache hierarchy, and our full-system proof is the first machine verification of sequential consistency for a multicore hardware design that includes caches and speculative processors. Keywords: Hardware Design; Label Transition System; Speculative Load; Program Counter; Coherence State | en_US |
dc.description.sponsorship | National Science Foundation (U.S.) (Grant CCF-1253229) | en_US |
dc.description.sponsorship | Air Force Office of Scientific Research (Contract FA8750-11-C-0249) | en_US |
dc.language.iso | en | |
dc.publisher | Springer International Publishing | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1007/978-3-319-21668-3_7 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Prof. Chlipala via Phoebe Ayers | en_US |
dc.title | Modular Deductive Verification of Multiprocessor Hardware Designs | en_US |
dc.type | Book | en_US |
dc.identifier.citation | Vijayaraghavan, Muralidaran et al. "Modular Deductive Verification of Multiprocessor Hardware Designs." CAV 2015: Computer Aided Verification (July 2015): 109-127 © 2015 Springer International Publishing Switzerland | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory | en_US |
dc.relation.journal | CAV 2015: Computer Aided Verification | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dc.date.updated | 2019-10-04T16:34:54Z | |
dspace.date.submission | 2019-10-04T16:34:55Z | |