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A −80dBm BLE-compliant, FSK wake-up receiver with system and within-bit dutycycling for scalable power and latency

Author(s)
Abdelhamid, Mohamed Radwan; Paidimarri, Arun; Chandrakasan, Anantha P
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DownloadBLE_WuRx_CICC.pdf (624.1Kb)
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Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/
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Abstract
This paper presents an FSK wake-up receiver with a -80 dBm sensitivity using a packet structure and a duty cycling scheme compliant with the Bluetooth Low Energy (BLE) protocol trading off power with latency. Event-driven applications achieve power lower than 240nW from a 0.75V supply while latency-critical systems wake up in almost 200μW at a 230μW consumption. A within-bit LC oscillator duty-cycling scheme is proposed to provide an extra 24% power reduction. Additionally, a custom FSK transmitter can trigger wake-up at 17nW only for an average latency of 5 seconds.
Date issued
2018-05
URI
https://hdl.handle.net/1721.1/122625
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Journal
2018 IEEE Custom Integrated Circuits Conference (CICC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Abdelhamid, Mohamed et al. "A −80dBm BLE-compliant, FSK wake-up receiver with system and within-bit dutycycling for scalable power and latency." 2018 IEEE Custom Integrated Circuits Conference (CICC), April 2018, San Diego, California, USA, Institute of Electrical and Electronics Engineers (IEEE), May 2018 © 2018 IEEE
Version: Author's final manuscript
ISBN
9781538624838
ISSN
2152-3630

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