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dc.contributor.authorZhang, Cheng
dc.contributor.authorPerreault, David J
dc.date.accessioned2020-01-21T19:49:31Z
dc.date.available2020-01-21T19:49:31Z
dc.date.issued2018-09
dc.date.submitted2018-06
dc.identifier.isbn9781538655412
dc.identifier.urihttps://hdl.handle.net/1721.1/123498
dc.description.abstractBoost converters running in valley switching mode have the advantages of low switching loss and small inductor size. However, the switching frequency is not fixed as operating conditions vary, which can make inductor design for this converter challenging. In this paper, a systematic optimization approach is presented that is suitable for wide-input-voltage range designs such as power factor correction (PFC) converters. The loss of each component is modeled as a function of the operating point, and the efficiency is estimated over the entire input voltage range. Given a set of selected cores and Litz wire, an optimal inductor design can be found on a plot of efficiencies and air-gap lengths. Genetic algorithms can be used to find the optimal design with customizable cores. Experiments are conducted to verify the model and the approach. One of the prototypes, designed as the first stage for an ac-dc converter system, achieves around 98% efficiency over the input range of 70V to 170V, boosting to 363V at 45W. The prototype converter has a total volume of 2.8cm³ and reaches a power density of 263W/in³ .en_US
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/compel.2018.8460066en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceProf. Perreault via Phoebe Ayersen_US
dc.titleAn optimization approach for high-efficiency high-power-density boost convertersen_US
dc.typeArticleen_US
dc.identifier.citationZhang, Cheng and David J. Perreault. "An optimization for high-efficiency high-power-density boost converters." 2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL), June 2018, Padua Italy, Institute of Electrical and Electronics Engineers (IEEE), September 2018 © 2018 IEEEen_US
dc.contributor.departmentMassachusetts Institute of Technology. Research Laboratory of Electronicsen_US
dc.relation.journal2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2020-01-15T19:10:20Z
dspace.date.submission2020-01-15T19:10:22Z
mit.metadata.statusComplete


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