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Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
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The integration of III-V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI-GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI-GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.
Date issued
2016-07Department
Singapore-MIT Alliance in Research and Technology (SMART); Massachusetts Institute of Technology. Department of Materials Science and EngineeringJournal
Applied Physics Express
Publisher
Japan Society of Applied Physics
Citation
Lee, Kwang Hong et al. "Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process." Applied Physics Express, 9, 8 (July 2016) © 2016 The Japan Society of Applied Physics.
Version: Author's final manuscript
ISSN
1882-0778
1882-0786