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dc.contributor.authorKiriansky, Vladimir L.(Vladimir Lubenov)
dc.contributor.authorLebedev, Ilia A.
dc.contributor.authorAmarasinghe, Saman P
dc.contributor.authorDevadas, Srinivas
dc.contributor.authorEmer, Joel S
dc.date.accessioned2020-03-27T15:13:03Z
dc.date.available2020-03-27T15:13:03Z
dc.date.issued2018-12
dc.date.submitted2018-10
dc.identifier.isbn9781538662403
dc.identifier.urihttps://hdl.handle.net/1721.1/124388
dc.description.abstractSoftware side channel attacks have become a serious concern with the recent rash of attacks on speculative processor architectures. Most attacks that have been demonstrated exploit the cache tag state as their exfiltration channel. While many existing defense mechanisms that can be implemented solely in software have been proposed, these mechanisms appear to patch specific attacks, and can be circumvented. In this paper, we propose minimal modifications to hardware to defend against a broad class of attacks, including those based on speculation, with the goal of eliminating the entire attack surface associated with the cache state covert channel. We propose DAWG, Dynamically Allocated Way Guard, a generic mechanism for secure way partitioning of set associative structures including memory caches. DAWG endows a set associative structure with a notion of protection domains to provide strong isolation. When applied to a cache, unlike existing quality of service mechanisms such as Intel's Cache Allocation Technology (CAT), DAWG fully isolates hits, misses, and metadata updates across protection domains. We describe how DAWG can be implemented on a processor with minimal modifications to modern operating systems. We describe a non-interference property that is orthogonal to speculative execution and therefore argue that existing attacks such as Spectre Variant 1 and 2 will not work on a system equipped with DAWG. Finally, we evaluate the performance impact of DAWG on the cache subsystem.en_US
dc.description.sponsorshipNSF (Grant CNS-1413920)en_US
dc.description.sponsorshipDARPA (Contract HR001118C0018)en_US
dc.description.sponsorshipDARPA (Contract HR00111830007)en_US
dc.description.sponsorshipDARPA (Contract FA87501720126)en_US
dc.description.sponsorshipDoE (Award DE-FOA0001059)en_US
dc.description.sponsorshipToyota (Grant LP-C000765-SR)en_US
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/micro.2018.00083en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceOther repositoryen_US
dc.titleDAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processorsen_US
dc.typeArticleen_US
dc.identifier.citationKiriansky, Vladimir et al. "DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors."51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2018, Institute of Electrical and Electronics Engineers (IEEE), December 2018 © 2018 IEEEen_US
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratoryen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.relation.journal51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2019-05-28T16:58:24Z
dspace.date.submission2019-05-28T16:58:25Z
mit.metadata.statusComplete


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