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dc.contributor.authorZhao, Qing-Yuan
dc.contributor.authorToomey, Emily Anne
dc.contributor.authorButters, Brendan Andrew
dc.contributor.authorMcCaughan, Adam N.
dc.contributor.authorDane, Andrew E.
dc.contributor.authorNam, Sae-Woo
dc.contributor.authorBerggren, Karl K.
dc.date.accessioned2020-04-22T02:37:34Z
dc.date.available2020-04-22T02:37:34Z
dc.date.issued2018-02
dc.identifier.issn0953-2048
dc.identifier.urihttps://hdl.handle.net/1721.1/124775
dc.description.abstractA superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10[superscript -19] J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm ×7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.en_US
dc.description.sponsorshipUnited States. National Aeronautics and Space Administration (Research Fellowship Award NNX14AL48H)en_US
dc.description.sponsorshipNational Science Foundation (U.S.) Graduate Research Fellowship Program (Grant 1122374)en_US
dc.language.isoen
dc.publisherIOP Publishingen_US
dc.relation.isversionofhttp://dx.doi.org/10.1088/1361-6668/AAA820en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourcearXiven_US
dc.titleA compact superconducting nanowire memory element operated by nanowire cryotronsen_US
dc.typeArticleen_US
dc.identifier.citationZhao, Qing-Yuan, et al. “A Compact Superconducting Nanowire Memory Element Operated by Nanowire Cryotrons.” Superconductor Science and Technology 31, 3 (July 2018): 035009.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.relation.journalSuperconductor Science and Technologyen_US
dc.eprint.versionOriginal manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2019-05-08T17:04:02Z
dspace.date.submission2019-05-08T17:04:03Z
mit.journal.volume31en_US
mit.journal.issue3en_US
mit.metadata.statusComplete


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