dc.contributor.author | Hanson, Alex J. | |
dc.contributor.author | Martin, Andreea F. | |
dc.contributor.author | Perreault, David J. | |
dc.date.accessioned | 2020-05-06T18:58:19Z | |
dc.date.available | 2020-05-06T18:58:19Z | |
dc.date.issued | 2019-11 | |
dc.date.submitted | 2019-02 | |
dc.identifier.issn | 0885-8993 | |
dc.identifier.issn | 1941-0107 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/125070 | |
dc.description.abstract | Grid-interface converters with power factor correction (PFC) generally require large energy buffer capacitors to maintain a constant power output. These buffer capacitors can occupy 20%-30% of total system volume, and their size is unaffected by typical methods of miniaturizing power converters such as increasing efficiency or changing switching frequency. Here, we investigate an approach in which harmonic current is intentionally drawn from the grid (within allowed regulations) to reduce the required energy storage. We show that this method can substantially reduce the energy storage requirement under every IEC/EN 61000-3-2 regulation class, including Class A (>60% reduction), Class B (>80%), Class C >25 W (>25%), Class C ≤q 25 W (>70%), and Class D (62%). This benefit can generally be achieved solely through controls without additional hardware and can be applied across PFC converter topologies. A valley-switched boost PFC converter is used to validate that harmonic injection achieves the calculated energy storage reduction with little impact on efficiency. We also show that, for a variable-frequency PFC, the proposed approach beneficially compresses the switching frequency range. This technique, thus, provides a high-impact, low-cost approach to miniaturizing the energy buffer in grid-interface power converters. | en_US |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/TPEL.2019.2900021 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Prof. Perreault via Phoebe Ayers | en_US |
dc.title | Energy and Size Reduction of Grid-Interfaced Energy Buffers Through Line Waveform Control | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Hanson, Alex J. et al. "Energy and Size Reduction of Grid-Interfaced Energy Buffers Through Line Waveform Control." IEEE Transactions on Power Electronics 34, 11 (November 2019): 111442-11453 © 2020 IEEE | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.relation.journal | IEEE Transactions on Power Electronics | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dc.date.updated | 2020-01-14T18:09:59Z | |
dspace.date.submission | 2020-01-14T18:10:02Z | |
mit.journal.volume | 34 | en_US |
mit.journal.issue | 11 | en_US |
mit.metadata.status | Complete | |