dc.contributor.author | Wang, Miaorong | |
dc.contributor.author | Chandrakasan, Anantha P | |
dc.date.accessioned | 2020-06-16T19:18:41Z | |
dc.date.available | 2020-06-16T19:18:41Z | |
dc.date.issued | 2020-04 | |
dc.date.submitted | 2019-11 | |
dc.identifier.isbn | 9781728151069 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/125824 | |
dc.description.abstract | To support various edge applications, a neural network accelerator needs to achieve high flexibility and classification accuracy within a limited power budget. This paper proposes a weight tuning algorithm to improve the energy efficiency by lowering the switching activity. A flexible and runtime-reconfigurable CNN accelerator is co-designed with the algorithm and demonstrated with a feature extraction processor on an FPGA. The system is fully self-contained for small CNNs and speech keyword spotting is shown as an example. A fully integrated custom ASIC is also being fabricated for this system. Based on post place-and-route simulation of the ASIC, the weight tuning algorithm reduces the energy consumption of weight delivery and computation by 1.70x and 1.20x respectively with little loss in accuracy. | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/a-sscc47793.2019.9056941 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Utsav Banerjee | en_US |
dc.title | Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Wang, Miaorong and Anantha P. Chandrakasan. "Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning." IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2019, Macau, Macao, Institute of Electrical and Electronics Engineers (IEEE), April 2020 | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.relation.journal | IEEE Asian Solid-State Circuits Conference (A-SSCC) | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dspace.date.submission | 2020-06-09T21:48:07Z | |
mit.journal.issue | 2019 | en_US |
mit.license | OPEN_ACCESS_POLICY | |
mit.metadata.status | Complete | |