| dc.contributor.author | Lu, Wenjie | |
| dc.contributor.author | Roh, I. P. | |
| dc.contributor.author | Geum, D.-M. | |
| dc.contributor.author | Kim, S.-H. | |
| dc.contributor.author | Song, J. D. | |
| dc.contributor.author | Kong, L. | |
| dc.contributor.author | del Alamo, Jesus A | |
| dc.date.accessioned | 2020-07-15T14:57:03Z | |
| dc.date.available | 2020-07-15T14:57:03Z | |
| dc.date.issued | 2018-01 | |
| dc.date.submitted | 2017-12 | |
| dc.identifier.isbn | 9781538635599 | |
| dc.identifier.issn | 2156-017X | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/126200 | |
| dc.description.abstract | We have fabricated self-aligned InGaSb p-channel FinFETs using a novel antimonide-compatible digital etch. This is the first demonstration of digital etch on InGaSb-based transistors of any kind. It has enabled the first fabricated InGaSb FinFETs featuring fin widths down to 10 nm and gate lengths of 20 nm. Single fin transistors with Wf = 10 nm and channel height of 23 nm (fin aspect ratio of 2.3) have achieved a record transconductance of 160 μS/μm at V ds = 0.5 V. When normalized to device footprint, it reaches a record high gm = 704 μS/μm. Digital etch has been shown to effectively improve the turn-off characteristics of the devices. | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1109/iedm.2017.8268412 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | Prof. del Alamo via Phoebe Ayers | en_US |
| dc.title | 10-nm Fin-width InGaSb p-channel self-aligned FinFETs using antimonide-compatible digital etch | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Lu, W. et al. "10-nm Fin-width InGaSb p-channel self-aligned FinFETs using antimonide-compatible digital etch." IEEE International Electron Devices Meeting (IEDM), December 2017, San Francisco, CA, USA, Institute of Electrical and Electronics Engineers (IEEE), January 2018 © 2017 IEEE | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Microsystems Technology Laboratories | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.relation.journal | IEEE International Electron Devices Meeting (IEDM) | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/ConferenceItem | en_US |
| eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
| dspace.date.submission | 2020-07-10T18:22:52Z | |
| mit.license | OPEN_ACCESS_POLICY | |
| mit.metadata.status | Complete | |