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dc.contributor.authorZhang, Guowei
dc.contributor.authorSanchez, Daniel
dc.date.accessioned2020-11-17T15:50:08Z
dc.date.available2020-11-17T15:50:08Z
dc.date.issued2017-10
dc.identifier.issn1556-6056
dc.identifier.urihttps://hdl.handle.net/1721.1/128501
dc.description.abstractMemoization improves performance and saves energy by caching and reusing the outputs of repetitive computations. Prior work has proposed software and hardware memoization techniques, but both have significant drawbacks. Software memoization suffers from high runtime overheads, and is thus limited to long computations. Conventional hardware memoization techniques achieve low overheads and can memoize short functions, but they rely on large, special-purpose memoization caches that waste significant area and energy. We propose MCACHE, a hardware technique that leverages data caches for memoization. MCACHE stores memoization tables in memory, and allows them to share cache capacity with normal program data. MCACHE introduces ISA and pipeline extensions to accelerate memoization operations, bridging the gap between software and conventional hardware techniques. Simulation results show that MCACHE improves performance by up to 21 ×, outperforms software memoization by up to 2.2 ×, and achieves similar or superior performance over conventional hardware techniques without any dedicated storage.en_US
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/lca.2017.2762308en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT web domainen_US
dc.titleLeveraging Hardware Caches for Memoizationen_US
dc.typeArticleen_US
dc.identifier.citationZhang, Guowei and Daniel Sanchez. "Leveraging Hardware Caches for Memoization." IEEE Computer Architecture Letters 17, 1 (January 2018): 59-63 © 2017 IEEEen_US
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratoryen_US
dc.relation.journalIEEE Computer Architecture Lettersen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dc.date.updated2019-07-03T13:36:26Z
dspace.date.submission2019-07-03T13:36:26Z
mit.journal.volume17en_US
mit.journal.issue1en_US
mit.metadata.statusComplete


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