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Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies

Author(s)
Tsai, Po-An; Chen, Changping; Sanchez, Daniel
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Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/
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Abstract
Conventional multicores rely on deep cache hierarchies to reduce data movement. Recent advances in die stacking have enabled near-data processing (NDP) systems that reduce data movement by placing cores close to memory. NDP cores enjoy cheaper memory accesses and are more area-constrained, so they use shallow cache hierarchies instead. Since neither shallow nor deep hierarchies work well for all applications, prior work has proposed systems that incorporate both. These asymmetric memory hierarchies can be highly beneficial, but they require scheduling computation to the right hierarchy. We present AMS, an adaptive scheduler that automatically finds high-quality thread-To-hierarchy mappings. AMS monitors threads, accurately models their performance under different hierarchies and core types, and adapts algorithms first proposed for cache partitioning to produce high-quality schedules. AMS is cheap enough to use online, so it adapts to program phases, and performs within 1% of an exhaustive-search scheduler. As a result, AMS outperforms asymmetry-oblivious schedulers by up to 37% and by 18% on average.
Date issued
2018-12
URI
https://hdl.handle.net/1721.1/128653
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Journal
51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Tsai, Po-An et al. "Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies." 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2018, Fukuoka, Japan, Institute of Electrical and Electronics Engineers (IEEE), December 2018. © 2018 IEEE
Version: Author's final manuscript
ISBN
9781538662403

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