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dc.contributor.authorGhobadi, Manya
dc.date.accessioned2021-01-22T16:08:46Z
dc.date.available2021-01-22T16:08:46Z
dc.date.issued2019-11
dc.identifier.issn2167-4329
dc.identifier.urihttps://hdl.handle.net/1721.1/129527
dc.description.abstractAs bytes-per-FLOP ratios continue to decline, communication is becoming a bottleneck for performance scaling. This paper describes bandwidth steering in HPC using emerging reconfigurable silicon photonic switches. We demonstrate that placing photonics in the lower layers of a hierarchical topology efficiently changes the connectivity and consequently allows operators to recover from system fragmentation that is otherwise hard to mitigate using common task placement strategies. Bandwidth steering enables efficient utilization of the higher layers of the topology and reduces cost with no performance penalties. In our simulations with a few thousand network endpoints, bandwidth steering reduces static power consumption per unit throughput by 36% and dynamic power consumption by 14% compared to a reference fat tree topology. Such improvements magnify as we taper the bandwidth of the upper network layer. In our hardware testbed, bandwidth steering improves total application execution time by 69%, unaffected by bandwidth tapering.en_US
dc.description.sponsorshipUnited States. Advanced Research Projects Agency-Energy. ENLITENED Program (Project award DE-AR00000843)en_US
dc.description.sponsorshipUnited States. Department of Energy. Office of Science ( Contract DE-AC02-05CH11231)en_US
dc.language.isoen
dc.publisherAssociation for Computing Machinery (ACM)en_US
dc.relation.isversionof10.1145/3295500.3356145en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT web domainen_US
dc.titleBandwidth steering in HPC using silicon nanophotonicsen_US
dc.typeArticleen_US
dc.identifier.citationMichelogiannakis, George et al. “Bandwidth steering in HPC using silicon nanophotonics.” International Conference for High Performance Computing, Networking, Storage and Analysis, SC, 2019 (November 2019): 17–22 © 2019 The Author(s)en_US
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratoryen_US
dc.relation.journalInternational Conference for High Performance Computing, Networking, Storage and Analysis, SCen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2020-12-15T15:52:27Z
dspace.orderedauthorsMichelogiannakis, G; Shen, Y; Teh, MY; Meng, X; Aivazi, B; Groves, T; Shalf, J; Glick, M; Ghobadi, M; Dennison, L; Bergman, Ken_US
dspace.date.submission2020-12-15T15:52:33Z
mit.journal.volume2019en_US
mit.licenseOPEN_ACCESS_POLICY
mit.metadata.statusComplete


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