| dc.contributor.author | Sze, Vivienne | |
| dc.contributor.author | Chen, Yu-Hsin | |
| dc.contributor.author | Yang, Tien-Ju | |
| dc.contributor.author | Emer, Joel S | |
| dc.date.accessioned | 2021-03-09T19:08:18Z | |
| dc.date.available | 2021-03-09T19:08:18Z | |
| dc.date.issued | 2020-08 | |
| dc.identifier.issn | 1943-0582 | |
| dc.identifier.issn | 1943-0590 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/130112 | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1109/mssc.2020.3002140 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | Prof. Sze via Phoebe Ayers | en_US |
| dc.subject | Electrical and Electronic Engineering | en_US |
| dc.title | How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Sze, Vivienne et al. "How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful." IEEE Solid-State Circuits Magazine 12, 3 (August 2020): 28 - 41. © 2020 IEEE | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Microsystems Technology Laboratories | en_US |
| dc.relation.journal | IEEE Solid-State Circuits Magazine | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
| eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
| dspace.date.submission | 2021-03-05T15:32:10Z | |
| mit.journal.volume | 12 | en_US |
| mit.journal.issue | 3 | en_US |
| mit.license | OPEN_ACCESS_POLICY | |
| mit.metadata.status | Complete | |
