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dc.contributor.authorOusterhout, Amy Elizabeth
dc.contributor.authorFried, Joshua
dc.contributor.authorBehrens, Jonathan (Jonathan Kyle)
dc.contributor.authorBelay, Adam M
dc.contributor.authorBalakrishnan, Hari
dc.date.accessioned2021-06-17T19:10:35Z
dc.date.available2021-06-17T19:10:35Z
dc.date.issued2019-02
dc.identifier.urihttps://hdl.handle.net/1721.1/131018
dc.description.abstractDatacenter applications demand microsecond-scale tail latencies and high request rates from operating systems, and most applications handle loads that have high variance over multiple timescales. Achieving these goals in a CPU-efficient way is an open problem. Because of the high overheads of today's kernels, the best available solution to achieve microsecond-scale latencies is kernel-bypass networking, which dedicates CPU cores to applications for spin-polling the network card. But this approach wastes CPU: even at modest average loads, one must dedicate enough cores for the peak expected load. Shenango achieves comparable latencies but at far greater CPU efficiency. It reallocates cores across applications at very fine granularity-every 5 µs-enabling cycles unused by latency-sensitive applications to be used productively by batch processing applications. It achieves such fast reallocation rates with (1) an efficient algorithm that detects when applications would benefit from more cores, and (2) a privileged component called the IOKernel that runs on a dedicated core, steering packets from the NIC and orchestrating core reallocations. When handling latency-sensitive applications, such as memcached, we found that Shenango achieves tail latency and throughput comparable to ZygOS, a state-of-the-art, kernel-bypass network stack, but can linearly trade latency-sensitive application throughput for batch processing application throughput, vastly increasing CPU efficiency.en_US
dc.description.sponsorshipNSF (Grants CNS-1407470, CNS-1526791, CNS-1563826)en_US
dc.language.isoen
dc.publisherAssociation for Computing Machinery (ACM)/ USENIX Associationen_US
dc.relation.isversionofhttps://www.usenix.org/system/files/nsdi19-ousterhout.pdfen_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceProf. Belay via Phoebe Ayersen_US
dc.titleShenango: Achieving high CPU efficiency for latency-sensitive datacenter workloadsen_US
dc.typeArticleen_US
dc.identifier.citationOusterhout, Amy et al. "Shenango: Achieving high CPU efficiency for latency-sensitive datacenter workloads." Proceedings of the 16th USENIX Symposium on Networked Systems Design and Implementation, February 2019, Boston, MA, Association for Computing Machinery / USENIX Association, February 2019. © 2019 The USENIX Associationen_US
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratoryen_US
dc.relation.journalProceedings of the 16th USENIX Symposium on Networked Systems Design and Implementationen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2021-06-17T17:02:26Z
dspace.orderedauthorsOusterhout, A; Fried, J; Behrens, J; Belay, A; Balakrishnan, Hen_US
dspace.date.submission2021-06-17T17:02:28Z
mit.licenseOPEN_ACCESS_POLICY
mit.metadata.statusComplete


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