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dc.contributor.authorBanerjee, Utsav
dc.contributor.authorWright, Andrew D.
dc.contributor.authorJuvekar, Chiraag
dc.contributor.authorWaller, Madeleine(Madeleine G.)
dc.contributor.authorArvind, Arvind
dc.contributor.authorChandrakasan, Anantha P
dc.date.accessioned2021-08-26T13:37:09Z
dc.date.available2021-08-26T13:37:09Z
dc.date.issued2019-08
dc.identifier.issn0018-9200
dc.identifier.issn1558-173X
dc.identifier.urihttps://hdl.handle.net/1721.1/131206
dc.description.abstractThis paper presents the first hardware implementation of the datagram transport layer security (DTLS) protocol to enable end-to-end security for the Internet of Things (IoT). A key component of this design is a reconfigurable prime field elliptic curve cryptography (ECC) accelerator that is 238× and 9× more energy-efficient compared to software and state-of-the-art hardware, respectively. Our full hardware implementation of the DTLS 1.3 protocol provides 438× improvement in energy-efficiency over software, along with code size and data memory usage as low as 8 and 3 KB, respectively. The cryptographic accelerators are coupled with an on-chip low-power RISC-V processor to benchmark applications beyond DTLS with up to two orders of magnitude energy savings. The test chip, fabricated in 65-nm CMOS, demonstrates hardware-accelerated DTLS sessions while consuming 44.08 μJ/handshake and 0.89 nJ/byte of the encrypted data at 16 MHz and 0.8 V.en_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/jssc.2019.2915203en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceUtsav Banerjeeen_US
dc.titleAn Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applicationsen_US
dc.typeArticleen_US
dc.identifier.citationBanerjee, Utsav et al. "An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications." IEEE Journal of Solid-State Circuits 54, 8 (August 2019): 2339 - 2352. © 2019 IEEEen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverBanerjee, Utsaven_US
dc.relation.journalIEEE Journal of Solid-State Circuitsen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.date.submission2021-08-12T12:33:35Z
mit.journal.volume54en_US
mit.journal.issue8en_US
mit.licenseOPEN_ACCESS_POLICY
mit.metadata.statusCompleteen_US
mit.metadata.statusComplete


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