Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications

Abstract

Abstract This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual sensor networks (VSN) or Internet of Multimedia Things (IoMT). The main feature of the proposed architecture is the novel data scanning technique that makes memory requirement independent of the image size. The proposed architecture needs only (30S) words of memory, where S is the number of parallel processing units and a critical path delay (CPD) equal to the delay of a multiplier (Tm). Furthermore, a multiplierless version of this architecture is also proposed which reduces the CPD to Ta<Tm (where Ta is the delay of an adder). In order to evaluate their effectiveness, the proposed architectures are coded in HDL and implemented on same FPGA board. Their performance is also compared with other state-of-the-art low memory DWT architectures. The experimental results show the superiority of the proposed architectures in terms of memory and CPD compared to existing DWT architectures. Moreover, the reduction in CPD to Ta indicates that the operating frequency can be scaled up by several factors and can be chosen depending upon the application. Compared to one of the best state-of-the-art DWT architecture, proposed multiplierless architecture (with S = 4) needs 57.37% less LUT’s and 64.39% less flip-flops for HR image of dimension 2048 × 2048. Moreover, the proposed architecture needs no LUTRAM and DSP, whereas the existing architecture requires 3264 LUTRAM and 24 DSP’s. Thus the proposed multiplierless architecture is superior to the existing state-of-the-art architecture and is suitable for IoMT/VSNs.