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This is not the latest version of this item. The latest version can be found at:https://dspace.mit.edu/handle/1721.1/132169.2
Building Manycore Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics
| dc.date.accessioned | 2021-09-20T18:21:14Z | |
| dc.date.available | 2021-09-20T18:21:14Z | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/132169 | |
| dc.language.iso | en | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | 10.1109/MM.2009.51 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | other univ website | en_US |
| dc.title | Building Manycore Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics | en_US |
| dc.type | Article | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
| eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
| dc.date.updated | 2019-07-02T14:54:00Z | |
| dspace.date.submission | 2019-07-02T14:54:01Z | |
| mit.metadata.status | Authority Work and Publication Information Needed |
