Show simple item record

dc.contributor.authorBlelloch, Guy E
dc.contributor.authorGibbons, Phillip B
dc.contributor.authorGu, Yan
dc.contributor.authorMcGuffey, Charles
dc.contributor.authorShun, Julian
dc.date.accessioned2021-10-27T20:10:24Z
dc.date.available2021-10-27T20:10:24Z
dc.date.issued2018
dc.identifier.urihttps://hdl.handle.net/1721.1/135028
dc.description.abstract© 2018 Association for Computing Machinery. We consider a parallel computational model, the Parallel Persistent Memory model, comprised of P processors, each with a fast local ephemeral memory of limited size, and sharing a large persistent memory. The model allows for each processor to fault at any time (with bounded probability), and possibly restart. When a processor faults, all of its state and local ephemeral memory is lost, but the persistent memory remains. This model is motivated by upcoming non-volatile memories that are nearly as fast as existing random access memory, are accessible at the granularity of cache lines, and have the capability of surviving power outages. It is further motivated by the observation that in large parallel systems, failure of processors and their caches is not unusual. We present several results for the model, using an approach that breaks a computation into capsules, each of which can be safely run multiple times. For the single-processor version we describe how to simulate any program in the RAM, the external memory model, or the ideal cache model with an expected constant factor overhead. For the multiprocessor version we describe how to efficiently implement a work-stealing scheduler within the model such that it handles both soft faults, with a processor restarting, and hard faults, with a processor permanently failing. For any multithreaded fork-join computation that is race free, write-after-read conflict free and has W work, D depth, and C maximum capsule work in the absence of faults, the scheduler guarantees a time bound on the model of OPWA + DPPAjlog1/(Cf) Wk in expectation, where P is the maximum number of processors, PA is the average number, and f ≤ 1/(2C) is the probability a processor faults between successive persistent memory accesses. Within the model, and using the proposed methods, we develop efficient algorithms for parallel prefix sums, merging, sorting, and matrix multiply.
dc.language.isoen
dc.publisherAssociation for Computing Machinery (ACM)
dc.relation.isversionof10.1145/3210377.3210381
dc.rightsCreative Commons Attribution-Noncommercial-Share Alike
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/
dc.sourceMIT web domain
dc.titleThe Parallel Persistent Memory Model
dc.typeArticle
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
dc.relation.journalAnnual ACM Symposium on Parallelism in Algorithms and Architectures
dc.eprint.versionAuthor's final manuscript
dc.type.urihttp://purl.org/eprint/type/ConferencePaper
eprint.statushttp://purl.org/eprint/status/NonPeerReviewed
dc.date.updated2019-07-03T14:45:45Z
dspace.orderedauthorsBlelloch, GE; Gibbons, PB; Gu, Y; McGuffey, C; Shun, J
dspace.date.submission2019-07-03T14:45:46Z
mit.metadata.statusAuthority Work and Publication Information Needed


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record