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dc.contributor.authorDhulipala, Laxman
dc.contributor.authorMcGuffey, Charles
dc.contributor.authorKang, Hongbo
dc.contributor.authorGu, Yan
dc.contributor.authorBlelloch, Guy E
dc.contributor.authorGibbons, Phillip B
dc.contributor.authorShun, Julian
dc.date.accessioned2021-10-27T20:35:37Z
dc.date.available2021-10-27T20:35:37Z
dc.date.issued2020
dc.identifier.urihttps://hdl.handle.net/1721.1/136483
dc.description.abstract© 2020, VLDB Endowment. Non-volatile main memory (NVRAM) technologies provide an attractive set of features for large-scale graph analytics, including byte-addressability, low idle power, and improved memory-density. NVRAM systems today have an order of magnitude more NVRAM than traditional memory (DRAM). NVRAM systems could therefore potentially allow very large graph problems to be solved on a single machine, at a modest cost. However, a significant challenge in achieving high performance is in accounting for the fact that NVRAM writes can be much more expensive than NVRAM reads. In this paper, we propose an approach to parallel graph analytics using the Parallel Semi-Asymmetric Model (PSAM), in which the graph is stored as a read-only data structure (in NVRAM), and the amount of mutable memory is kept proportional to the number of vertices. Similar to the popular semi-external and semi-streaming models for graph analytics, the PSAM approach assumes that the vertices of the graph fit in a fast read-write memory (DRAM), but the edges do not. In NVRAM systems, our approach eliminates writes to the NVRAM, among other benefits. To experimentally study this new setting, we develop Sage, a parallel semi-asymmetric graph engine with which we implement provably-efficient (and often work-optimal) PSAM algorithms for over a dozen fundamental graph problems. We experimentally study Sage using a 48-core machine on the largest publicly-available realworld graph (the Hyperlink Web graph with over 3.5 billion vertices and 128 billion edges) equipped with Optane DC Persistent Memory, and show that Sage outperforms the fastest prior systems designed for NVRAM. Importantly, we also show that Sage nearly matches the fastest prior systems running solely in DRAM, by effectively hiding the costs of repeatedly accessing NVRAM versus DRAM.
dc.language.isoen
dc.publisherVLDB Endowment
dc.relation.isversionof10.14778/3397230.3397251
dc.rightsCreative Commons Attribution-NonCommercial-NoDerivs License
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.sourceVLDB Endowment
dc.titleSage: parallel semi-asymmetric graph algorithms for NVRAMs
dc.typeArticle
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
dc.relation.journalProceedings of the VLDB Endowment
dc.eprint.versionFinal published version
dc.type.urihttp://purl.org/eprint/type/ConferencePaper
eprint.statushttp://purl.org/eprint/status/NonPeerReviewed
dc.date.updated2021-03-19T14:04:58Z
dspace.orderedauthorsDhulipala, L; McGuffey, C; Kang, H; Gu, Y; Blelloch, GE; Gibbons, PB; Shun, J
dspace.date.submission2021-03-19T14:04:59Z
mit.journal.volume13
mit.journal.issue9
mit.licensePUBLISHER_CC
mit.metadata.statusAuthority Work and Publication Information Needed


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