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First Demonstration of a Self-Aligned GaN p-FET
dc.contributor.author | Chowdhury, Nadim | |
dc.contributor.author | Xie, Qingyun | |
dc.contributor.author | Yuan, Mengyang | |
dc.contributor.author | Rajput, Nitul S | |
dc.contributor.author | Xiang, Peng | |
dc.contributor.author | Cheng, Kai | |
dc.contributor.author | Then, Han Wui | |
dc.contributor.author | Palacios, Tomas | |
dc.date.accessioned | 2021-11-01T18:35:34Z | |
dc.date.available | 2021-11-01T18:35:34Z | |
dc.date.issued | 2019 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/137036 | |
dc.description.abstract | © 2019 IEEE. In this work, we demonstrate a self-aligned p-FET with a GaN/Al0 2Ga0 8N (20 nm)/GaN heterostructure grown by metal-organic-chemical vapor deposition (MOCVD) on Si substrate. Our 100 nm channel length device with recess depth of 70 nm exhibits a record ON-resistance of 400 Ωmm and ON-current over 5 mA/mm with ON-OFF ratio of 6×105 when compared with other p-FET demonstrations based on GaN/AlGaN heterostructure. The device shows E-mode operation with a threshold voltage of -1 V, making it a promising candidate for GaN-based complementary circuit that can be integrated on a Silicon platform. A monolithically integrated n-channel transistor with p-GaN gate is also demonstrated. The potential of the reported p-FET for complementary logic application is evaluated through industry-standard compact modeling and inverter circuit simulation. | en_US |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | 10.1109/IEDM19573.2019.8993569 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Other repository | en_US |
dc.title | First Demonstration of a Self-Aligned GaN p-FET | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Chowdhury, Nadim, Xie, Qingyun, Yuan, Mengyang, Rajput, Nitul S, Xiang, Peng et al. 2019. "First Demonstration of a Self-Aligned GaN p-FET." Technical Digest - International Electron Devices Meeting, IEDM, 2019-December. | |
dc.relation.journal | Technical Digest - International Electron Devices Meeting, IEDM | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dc.date.updated | 2021-02-05T19:11:46Z | |
dspace.orderedauthors | Chowdhury, N; Xie, Q; Yuan, M; Rajput, NS; Xiang, P; Cheng, K; Then, HW; Palacios, T | en_US |
dspace.date.submission | 2021-02-05T19:11:50Z | |
mit.journal.volume | 2019-December | en_US |
mit.license | OPEN_ACCESS_POLICY | |
mit.metadata.status | Authority Work and Publication Information Needed | en_US |