Effects of a random process variation on the transfer characteristics of a fundamental photonic integrated circuit component

Abstract

© 2018 SPIE. Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS process variations and their effect on photonic component behavior. A key factor for the adoption of silicon photonics into high-yield manufacturing is to extend process design kits (PDKs) to include photonic process variability models that are aware of variations that may occur during the fabrication process. We study the effect of a well-known random process variation, line edge roughness (LER), present in the lithography and etch process, on the performance of a fundamental component, the Y-branch, through virtual fabrication simulations. Ideally, the Y-branch transmits the input power equally to its two output ports. However, imbalanced transmission between the two output ports is observed when LER is imposed on the Y-branch, depending on the statistical nature (amplitude and correlation length) of the LER. The imbalance can be as low as 1% for small LER amplitudes, and reach up to 15% for large LER amplitudes. In addition, LER increases the excess loss compared to the nominal (smooth) case. Ensemble statistical virtual fabrication and FDTD photonic simulations across a range of LER amplitude and correlation lengths are reported. These results can be captured as worst-case corner models and included in variation-aware photonic compact models.