R &D of back-end electronics for improved resistive plate chambers for the phase 2 upgrade of the CMS end-cap muon system

Abstract

Abstract

Purpose The Large Hadron Collider (LHC) at European Organization for Nuclear Research is planned to be upgraded to the high luminosity LHC. Increasing the luminosity makes muon triggering reliable and offline reconstruction very challenging. To enhance the redundancy of the Compact Muon Solenoid (CMS) Muon system and resolve the ambiguity of track reconstruction in the forward region, an improved Resistive Plate Chamber (iRPC) with excellent time resolution will be installed in the Phase-2 CMS upgrade. The iRPC will be equipped with Front-End Electronics (FEE), which can perform high-precision time measurements of signals from both ends of the strip. New Back-End Electronics (BEE) need to be researched and developed to provide sophisticated functionalities such as interacting with FEE with shared links for fast, slow control (SC) and data, in addition to trigger primitives (TPs) generation and data acquisition (DAQ).

Method The BEE prototype uses a homemade hardware board compatible with the MTCA standard, the back-end board (BEB). BEE interacts with FEE via a bidirectional 4.8 Gbps optical paired-link that integrates clock, data, and control information. The clock and fast/slow control commands are distributed from BEB to the FEE via the downlink. The uplink is used for BEB to receive the time information of the iRPC’s fired strips and the responses to the fast/slow control commands. To have a pipelined detector data for cluster finding operation, recover (DeMux) the time relationship of which is changed due to the transmission protocol for the continuous incoming MUXed data from FEE. Then at each bunch crossing (BX), clustering fired strips that satisfy time and spatial constraints to generate TPs. Both incoming raw MUXed detector data and TPs in a time window and latency based on the trigger signal are read out to the DAQ system. Gigabit Ethernet (GbE) of SiTCP and commercial 10-GbE are used as link standards for SC and DAQ, respectively, for the BEB to interact with the server.

Results The joint test results of the BEB with iRPC and Front-End Board (FEB) show a Bit Error Rate of the transmission links less than

$$1\times {10^{-16}}$$

1 ×

10

- 16

, a time resolution of the FEB Time-to-Digital Converter of 16 ps, and the resolution of the time difference between both ends of 160 ps which corresponding a spatial resolution of the iRPC of approximately 1.5 cm.

Conclusion Test results showed the correctness and stable running of the BEB prototype, of which the functionalities fulfill the iRPC requirements.