Circuit Analysis of Self-timed Elements for NMOS VLSI Systems

Abstract

Scalingof VLSI digital systems introduces new problems to the design of synchronous systems, due to the disproportional increase in wire delays with the decrease in transistor sizes. One the other hand, the asynchronous self-timed design approach, which has been traditionally less attractive, offer a number of advantages for VLSI. Also, this approach can be directly incorporated into a structured design methodology for Packet Communication Architectures. This paper considers a practical self-timed design methodology and studies its implementation in nMOS. The C-element and the arbiter circuit, two main circuit components of self-timed systems, are analyzed to allow the evaluation of the design approach.