MIT Libraries logoDSpace@MIT

MIT
View Item 
  • DSpace@MIT Home
  • Computer Science and Artificial Intelligence Lab (CSAIL)
  • LCS Publications
  • LCS Technical Memos (1974 - 2003)
  • View Item
  • DSpace@MIT Home
  • Computer Science and Artificial Intelligence Lab (CSAIL)
  • LCS Publications
  • LCS Technical Memos (1974 - 2003)
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed -Memory Multiprocess

Author(s)
Barua, Rajeev; Kranz, David; Agarwal, Anant
Thumbnail
DownloadMIT-LCS-TM-522.pdf (163.8Kb)
Metadata
Show full item record
Abstract
Harnessing the full performance potential of cache-coherent distributed shared memory multiprocessors without inordinate user effort requires a compilation technology that can automatically manage multiple levels of memory hierarchy. This paper describes a working compiler for such machines that automatically partitions loops and data arrays to optimize locality of access.
Date issued
1995-01
URI
https://hdl.handle.net/1721.1/149239
Series/Report no.
MIT-LCS-TM-522

Collections
  • LCS Technical Memos (1974 - 2003)

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

Login

Statistics

OA StatisticsStatistics by CountryStatistics by Department
MIT Libraries
PrivacyPermissionsAccessibilityContact us
MIT
Content created by the MIT Libraries, CC BY-NC unless otherwise noted. Notify us about copyright concerns.