Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine

Abstract

Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocessors are ill-suited to exploit such advances. Achieving a high level of parallelism at a reasonable clock speed requires distributing the processor resources - a trend already visible in the dual-register-file architecture of the Alpha 21264.