Artwork Analysis Tool for VLSI Circuits

Abstract

Current methods for designing VLSI chips do not insure that the chips will perform correctly when manufactured. Because the turn around time on chip fabrication varies from a few weeks to a few months, a scheme other than "try it and see if it works" is needed. Checking of chips by hand simulation and visual inspection of check plots will not cash all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years.This increase in complexity precludes any manual verification methods; some better method is needed.